Cita APA

Liang, X., Brooks, D., Canal, R., & Wei, G. Replacing 6T SRAMs with 3T1D DRAMs in the l1 data cache to combat process variability.

Citación estilo Chicago

Liang, Xiaoyao, David Brooks, Ramon Canal, y Gu-Yeon Wei. Replacing 6T SRAMs With 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.

Cita MLA

Liang, Xiaoyao, David Brooks, Ramon Canal, y Gu-Yeon Wei. Replacing 6T SRAMs With 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.