Liang, X., Brooks, D., Canal, R., & Wei, G. Replacing 6T SRAMs with 3T1D DRAMs in the l1 data cache to combat process variability.
Chicago Style CitationLiang, Xiaoyao, David Brooks, Ramon Canal, and Gu-Yeon Wei. Replacing 6T SRAMs With 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
MLA CitationLiang, Xiaoyao, David Brooks, Ramon Canal, and Gu-Yeon Wei. Replacing 6T SRAMs With 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
Warning: These citations may not always be 100% accurate.