Constraining Designs for Synthesis and Timing Analysis : A Practical Guide to Synopsys Design Constraints (SDC) - Gangadharan, Sridhar; Churiwala, Sanjay; SpringerLink (Online service) (New York, NY : Springer New York : Imprint: Springer, 2013)
Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC.
Keywords: Electronic circuits; Electronics; Microelectronics; Microprocessors; Circuits and Systems; Electronics and Microelectronics, Instrumentation; Processor Architectures