APA Citation

Taraate, V. (2019). Advanced HDL synthesis and SOC prototyping: RTL Design Using Verilog. Singapore: Springer.

Chicago Style Citation

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. Singapore: Springer, 2019.

MLA Citation

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. Singapore: Springer, 2019.

Warning: These citations may not always be 100% accurate.