Cita APA

Taraate, V. (2019). Advanced HDL synthesis and SOC prototyping: RTL Design Using Verilog. Singapore: Springer.

Citación estilo Chicago

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. Singapore: Springer, 2019.

Cita MLA

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. Singapore: Springer, 2019.

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