(2014). Design-for-test and test optimization techniques for TSV-based 3D stacked ICs.
Chicago Style CitationDesign-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs. 2014.
MLA CitationDesign-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs. 2014.
Warning: These citations may not always be 100% accurate.