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02082nam a22003135i 4500 |
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121204s2013 xxu| s |||| 0|eng d |
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|a 9781441995421
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| 024 |
7 |
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|a 10.1007/978-1-4419-9542-1
|2 doi
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| 040 |
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|a Sistema de Bibliotecas del Tecnológico de Costa Rica
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| 100 |
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|a Lim, Sung Kyu.
|e author.
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|a Design for High Performance, Low Power, and Reliable 3D Integrated Circuits /
|c by Sung Kyu Lim.
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| 250 |
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|a 1st ed. 2013.
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| 260 |
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|a New York, NY :
|b Springer New York :
|b Imprint: Springer,
|c 2013.
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| 300 |
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|a XXVIII, 560 p. :
|b online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
|2 rdacarrier
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|a Regular vs Irregular TSV Placementfor 3D IC -- Steiner Routingfor 3D IC -- Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC -- Power Delivery Network Design for 3D IC -- 3D Clock Routing for Pre-bond Testability -- TSV-to-TSV Coupling Analysis and Optimization -- TSV Current Crowding and Power Integrity -- Modeling of Atomic Concentration at the Wire-to-TSV Interface -- Multi-Objective Archetectural Floorplanning for 3D IC -- Thermal-aware Gate-level Placement for 3D IC -- 3D IC Cooling with Micro-Fluidic Channels -- Mechanical Reliability Analysis and Optimization for 3D IC -- Impact of Mechanical Stress on Timing Variation for 3D IC -- Chip/Package Co-Analysis of Mechanical Stress for 3D IC -- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations -- TSV Interfracial Crack Analysis and Optimization -- Ultra High Logic Designs Using Monolithic 3D Integration -- Impact of TSV Scaling on 3D IC Design Quality -- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.
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|a Electronic circuits.
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|a Nanotechnology.
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|a Microprocessors.
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|a Circuits and Systems.
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|a Nanotechnology and Microengineering.
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|a Processor Architectures.
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| 710 |
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|a SpringerLink (Online service)
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|t Springer eBooks
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