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101013s2010 xxu| s |||| 0|eng d |
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|a 9781441966001
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| 024 |
7 |
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|a 10.1007/978-1-4419-6600-1
|2 doi
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| 040 |
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|a Sistema de Bibliotecas del Tecnológico de Costa Rica
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| 100 |
1 |
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|a Cerny, Eduard.
|e author.
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| 245 |
1 |
4 |
|a The Power of Assertions in SystemVerilog /
|c by Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny.
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| 250 |
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|a 1st ed. 2010.
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| 260 |
# |
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|a New York, NY :
|b Springer US :
|b Imprint: Springer,
|c 2010.
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| 300 |
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|a XVII, 544 p. 166 illus. :
|b online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 505 |
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|a Opening -- SystemVerilog Language and Simulation Semantics Overview -- Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Let Sequence and Property Declarations Inference -- Advanced Properties -- Advanced Sequences -- to Assertion Based Formal Verification -- Formal Verification and Models -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Formal Semantics -- Checkers and Assertion Libraries -- Checkers -- Checkers in Formal Verification -- Checker Libraries -- Future Enhancements.
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| 650 |
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|a Electronic circuits.
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| 650 |
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|a Electrical engineering.
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| 650 |
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4 |
|a Circuits and Systems.
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| 650 |
2 |
4 |
|a Electrical Engineering.
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| 700 |
1 |
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|a Dudani, Surrendra.
|e author.
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| 700 |
1 |
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|a Havlicek, John.
|e author.
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| 700 |
1 |
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|a Korchemny, Dmitry.
|e author.
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| 710 |
2 |
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|a SpringerLink (Online service)
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| 773 |
0 |
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|t Springer eBooks
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| 900 |
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|a Libro descargado a ALEPH en bloque (proveniente de proveedor)
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