Low-Power High-Speed ADCs for Nanometer CMOS Integration
| Autores principales: | , |
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| Autor Corporativo: | |
| Formato: | eBook |
| Lenguaje: | English |
| Publicado: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
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| Edición: | 1st ed. 2008. |
| Colección: | Analog Circuits and Signal Processing,
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| Materias: | |
| Acceso en línea: | https://doi.org/10.1007/978-1-4020-8450-8 |
Tabla de Contenidos:
- A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS
- A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS
- A 0.4 ps-RMS-Jitter 1–3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification
- Conclusions and Future Directions.