Low-Power High-Speed ADCs for Nanometer CMOS Integration
| Main Authors: | , |
|---|---|
| Corporate Author: | |
| Format: | eBook |
| Language: | English |
| Published: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
|
| Edition: | 1st ed. 2008. |
| Series: | Analog Circuits and Signal Processing,
|
| Subjects: | |
| Online Access: | https://doi.org/10.1007/978-1-4020-8450-8 |
Table of Contents:
- A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS
- A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS
- A 0.4 ps-RMS-Jitter 1-3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification
- Conclusions and Future Directions.