Designing Reliable and Efficient Networks on Chips /

Detalles Bibliográficos
Autor principal: Murali, Srinivasan. (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: eBook
Lenguaje:English
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2009.
Edición:1st ed. 2009.
Colección:Lecture Notes in Electrical Engineering, 34
Materias:
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100 1 |a Murali, Srinivasan.  |e author. 
245 1 0 |a Designing Reliable and Efficient Networks on Chips /  |c by Srinivasan Murali. 
250 |a 1st ed. 2009. 
260 # # |a Dordrecht :  |b Springer Netherlands :  |b Imprint: Springer,  |c 2009. 
300 |a X, 198 p. :  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
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490 1 |a Lecture Notes in Electrical Engineering,  |v 34 
505 0 |a NoC Design Methods -- Designing Crossbar Based Systems -- Netchip Tool Flow for NoC Design -- Designing Standard Topologies -- Designing Custom Topologies -- Supporting Multiple Applications -- Supporting Dynamic Application Patterns -- NoC Reliability Mechanisms -- Timing-Error Tolerant NoC Design -- Analysis of NoC Error Recovery Schemes -- Fault-Tolerant Route Generation -- NoC Support for Reliable On-Chip Memories -- Conclusions and Future Directions. 
650 0 |a Electronic circuits. 
650 0 |a Power electronics. 
650 0 |a Microprocessors. 
650 1 4 |a Circuits and Systems. 
650 2 4 |a Power Electronics, Electrical Machines and Networks. 
650 2 4 |a Processor Architectures. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
900 |a Libro descargado a ALEPH en bloque (proveniente de proveedor)