Design, Automation, and Test in Europe : The Most Influential Papers of 10 Years DATE /

Detalles Bibliográficos
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Lauwereins, Rudy. (Editor ), Madsen, Jan. (Editor )
Formato: eBook
Lenguaje:English
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2008.
Edición:1st ed. 2008.
Materias:
Tabla de Contenidos:
  • System Level Design
  • System Level Design: Past, Present, and Future
  • Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems
  • EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability
  • RTOS Modeling for System Level Design
  • Context-Aware Performance Analysis for Efficient Embedded System Design
  • Lock-Free Synchronization for Dynamic Embedded Real-Time Systems
  • What If You Could Design Tomorrow’s System Today?
  • Networks on Chip
  • Networks on Chips
  • A Generic Architecture for On-Chip Packet-Switched Interconnections
  • Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
  • Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures
  • xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
  • A Network Traffic Generator Model for Fast Network-on-Chip Simulation
  • Modeling, Simulation and Run-Time Management
  • Modeling, Simulation and Run-Time Management
  • Dynamic Power Management for Nonstationary Service Requests
  • Quantitative Comparison of Power Management Algorithms
  • Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives
  • Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application
  • Compositional Specification of Behavioral Semantics
  • Design Technology for Advanced Digital Systems in CMOS and Beyond
  • Design Technology for Advanced Digital Systems in CMOS and Beyond
  • Address Bus Encoding Techniques for System-Level Power Optimization
  • MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
  • Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processors
  • Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
  • Physical Design and Validation
  • Physical Design and Validation
  • Interconnect Tuning Strategies for High-Performance ICs
  • Efficient Inductance Extraction via Windowing
  • Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
  • A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology
  • Test and Verification
  • The Test and Verification Influential Papers in the 10 Years of DATE
  • Cost Reduction and Evaluation of a Temporary Faults-Detecting Technique
  • An Integrated System-on-Chip Test Framework
  • Efficient Spectral Techniques for Sequential ATPG
  • BerkMin: A Fast and Robust Sat-Solver
  • Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-Chip Test Data Compression/Decompression
  • An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs.