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191106s2019 cr |sm 00| ||eng d |
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|a Sistema de Bibliotecas del Tecnológico de Costa Rica
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|a TF 8673
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|a Malavasi-Mora, Andrés
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|a Voltage drop tolerance by adaptive voltage scaling using clock-data compensation /
|c creador Andrés Malavasi-Mora.
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|a Cartago, Costa Rica :
|b A. Malavasi-M.,
|c 2019.
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|a 1 disco de computadora :
|b ilustraciones, diagramas, gráficas, tablas.
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|a texto
|b txt
|2 rdacontenido
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|a computadora
|b c
|2 rdamedio
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|a disco de computadora
|b cd
|2 rdaportador
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|a Tesis
|b (Maestría en Electrónica con énfasis en VLSI )
|c Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica,
|d 2019.
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|a Referencias
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|a Apéndice A: VDM considerations: delay line problem.
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|a Apéndice B: VDM Considerations: hold timing issues for “Previous Code” calculation.
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|a Apéndice C: VDM Behavior under different voltage drop frequencies.
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|a Apéndice D: Clock swing issues for VDM’s clock tree.
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|a ITCR
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|a COTA
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|a CSUCA
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|a ELEC
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|a Alta frecuencia
|2 Tesauro SIBITEC
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|a Microprocesadores,
|2 Tesauro SIBITEC
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|a Confiabilidad
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|a Rendimiento energético
|2 Tesauro SIBITEC
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|a Circuitos CMOS
|2 Tesauro SIBITEC
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|a Alta resistencia
|2 Tesauro SIBITEC
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|a Tesis
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|a Lisandro
|b 2020/06/01
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|a Lisandro
|b 2020/09/16
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