Voltage drop tolerance by adaptive voltage scaling using clock-data compensation /
| Autor principal: | |
|---|---|
| Formato: | Tesis Libro |
| Lenguaje: | English |
| Publicado: |
Cartago, Costa Rica :
A. Malavasi-M.,
2019.
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| Materias: |
Tabla de Contenidos:
- Apéndice A: VDM considerations: delay line problem.
- Apéndice B: VDM Considerations: hold timing issues for “Previous Code” calculation.
- Apéndice C: VDM Behavior under different voltage drop frequencies.
- Apéndice D: Clock swing issues for VDM’s clock tree.