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100301s2010 xxu| s |||| 0|eng d |
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|a 9781441909503
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| 024 |
7 |
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|a 10.1007/978-1-4419-0950-3
|2 doi
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| 040 |
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|a Sistema de Bibliotecas del Tecnológico de Costa Rica
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| 100 |
1 |
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|a Jayakumar, Nikhil.
|e author.
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|a Minimizing and Exploiting Leakage in VLSI Design /
|c by Nikhil Jayakumar, Suganth Paul, Rajesh Garg.
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| 250 |
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|a 1st ed. 2010.
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| 260 |
# |
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|a New York, NY :
|b Springer US :
|b Imprint: Springer,
|c 2010.
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| 300 |
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|a XXVII, 214 p. :
|b online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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|a Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results.
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|a Electronic circuits.
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|a Computer-aided engineering.
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|a Circuits and Systems.
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|a Computer-Aided Engineering (CAD, CAE) and Design.
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| 700 |
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|a Paul, Suganth.
|e author.
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| 700 |
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|a Garg, Rajesh.
|e author.
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| 710 |
2 |
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|a SpringerLink (Online service)
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| 773 |
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|t Springer eBooks
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| 900 |
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|a Libro descargado a ALEPH en bloque (proveniente de proveedor)
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