Minimizing and Exploiting Leakage in VLSI Design /
| Autores principales: | , , |
|---|---|
| Autor Corporativo: | |
| Formato: | eBook |
| Lenguaje: | English |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2010.
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| Edición: | 1st ed. 2010. |
| Materias: |
Tabla de Contenidos:
- Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes
- Existing Leakage Minimization Approaches
- Computing Leakage Current Distributions
- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities
- The HL Approach: A Low-Leakage ASIC Design Methodology
- Simultaneous Input Vector Control and Circuit Modification
- Optimum Reverse Body Biasing for Leakage Minimization
- I: Conclusions and Future Directions
- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design
- Exploiting Leakage: Sub-threshold Circuit Design
- Adaptive Body Biasing to Compensate for PVT Variations
- Optimum VDD for Minimum Energy
- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining
- II: Conclusions and Future Directions
- Design of a Sub-threshold BFSK Transmitter IC
- Design of the Chip
- Implementation of the Chip
- Experimental Results.