Advanced HDL synthesis and SOC prototyping : RTL Design Using Verilog.
| Formato: | Libro |
|---|---|
| Acceso en línea: | Ver documento en línea |
| LEADER | 00441nam a2200109 a 4500 | ||
|---|---|---|---|
| 001 | 000648635 | ||
| 005 | 20210810131109.0 | ||
| 008 | 210810 gr |||||| d | ||
| 020 | |a 9789811087769 |q (ebook) | ||
| 040 | |a Sistema de Bibliotecas de la Universidad de Costa Rica | ||
| 245 | 1 | 0 | |a Advanced HDL synthesis and SOC prototyping : |b RTL Design Using Verilog. |
| 856 | 4 | 1 | |u https://springerlink.proxyucr.elogim.com/book/10.1007/978-981-10-8776-9 |y Ver documento en línea |