Automatic analog IC sizing and optimization constrained with PVT corners and layout effects /

Similar Items

• Generating Analog IC Layouts with LAYGEN II /
  by: Martins, Ricardo M. F., et al.
  Published: (2013)
• AIDA-CMK: Multi-algorithm optimization kernel applied to analog IC sizing /
  by: Lourenço, Ricardo
  Published: (2015)
• CMOS IC layout. Concepts, methodologies, and tools /
  by: Clein, Dan
  Published: (1999)
• Analog layout synthesis : A survey of topological approaches.
• Analog IC reliability in nanometer CMOS /
  by: Maricau, Elie
  Published: (2013)