Automatic analog IC sizing and optimization constrained with PVT corners and layout effects /
| Formato: | Libro |
|---|---|
| Publicado: |
c2017.
|
| Acceso en línea: | Ver documento en línea |
| LEADER | 00532nam a2200121 a 4500 | ||
|---|---|---|---|
| 001 | 000659857 | ||
| 005 | 20211117172257.0 | ||
| 008 | 211117 2017 gr |||||| d | ||
| 020 | |a 9783319420370 |q (ebook) | ||
| 040 | |a Sistema de Bibliotecas de la Universidad de Costa Rica | ||
| 245 | 1 | 0 | |a Automatic analog IC sizing and optimization constrained with PVT corners and layout effects / |c Nuno Lourenço, Ricardo Martins, Nuno Horta. |
| 260 | |c c2017. | ||
| 856 | 4 | 1 | |u https://springerlink.proxyucr.elogim.com/book/10.1007/978-3-319-42037-0 |y Ver documento en línea |