Replacing 6T SRAMs with 3T1D DRAMs in the l1 data cache to combat process variability.
| Main Author: | |
|---|---|
| Other Authors: | , , |
| Format: | Article |
| Language: | Spanish |
| Subjects: |
Sistema de Bibliotecas del Tecnológico de Costa Rica
| Copy | Available |
|---|
| Main Author: | |
|---|---|
| Other Authors: | , , |
| Format: | Article |
| Language: | Spanish |
| Subjects: |
| Copy | Available |
|---|