Constraining Designs for Synthesis and Timing Analysis : A Practical Guide to Synopsys Design Constraints (SDC) /
| Autores principales: | , |
|---|---|
| Autor Corporativo: | |
| Formato: | eBook |
| Lenguaje: | English |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2013.
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| Edición: | 1st ed. 2013. |
| Materias: |
Tabla de Contenidos:
- Introduction
- Synthesis Basics
- Timing Analysis and Constraints
- SDC Extensions through Tcl
- Clocks
- Generated Clocks
- Clock Groups
- Other Clock Characteristics
- Port Delays
- Completing Port Constraints
- False Paths
- Multi Cycle Paths
- Combinatorial Paths
- Modal Analysis
- Managing Your Constraints
- Miscellaneous SDC Commands
- XDC: Xilinx Extensions To SDC.