Constraining Designs for Synthesis and Timing Analysis : A Practical Guide to Synopsys Design Constraints (SDC) /
| Main Authors: | , |
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| Corporate Author: | |
| Format: | eBook |
| Language: | English |
| Published: |
New York, NY :
Springer New York : Imprint: Springer,
2013.
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| Edition: | 1st ed. 2013. |
| Subjects: |
Table of Contents:
- Introduction
- Synthesis Basics
- Timing Analysis and Constraints
- SDC Extensions through Tcl
- Clocks
- Generated Clocks
- Clock Groups
- Other Clock Characteristics
- Port Delays
- Completing Port Constraints
- False Paths
- Multi Cycle Paths
- Combinatorial Paths
- Modal Analysis
- Managing Your Constraints
- Miscellaneous SDC Commands
- XDC: Xilinx Extensions To SDC.