Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Detalles Bibliográficos
Autores principales: Mohanty, Saraju P. (Autor), Ranganathan, Nagarajan. (Autor), Kougianos, Elias. (Autor), Patra, Priyardarsan. (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: eBook
Lenguaje:English
Publicado: New York, NY : Springer US : Imprint: Springer, 2008.
Edición:1st ed. 2008.
Materias:
Electronic circuits.
Electronics.
Microelectronics.
Computer-aided engineering.
Computer hardware.
Electrical engineering.
Circuits and Systems.
Electronics and Microelectronics, Instrumentation.
Computer-Aided Engineering (CAD, CAE) and Design.
Computer Hardware.
Electrical Engineering.
Acceso en línea:https://doi.org/10.1007/978-0-387-76474-0
Tabla de Contenidos:
  • High-Level Synthesis Fundamentals
  • Power Modeling and Estimation at Transistor and Logic Gate Levels
  • Architectural Power Modeling and Estimation
  • Power Reduction Fundamentals
  • Energy or Average Power Reduction
  • Peak Power Reduction
  • Transient Power Reduction
  • Leakage Power Reduction
  • Conclusions and Future Direction.

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