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Verificación lógica de los m...
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Verificación lógica de los modelos sintetizados para circuitos integrados. /
Bibliographic Details
Main Author:
González Rojas, José Daniel
Format:
Thesis
Book
Language:
Spanish
Published:
Cartago, Costa Rica :
J. González R.,
2010.
Subjects:
Circuitos integrados
Fallas lógicas
Rastreo
Verificación
Tesis
Holdings
Description
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