Replacing 6T SRAMs with 3T1D DRAMs in the l1 data cache to combat process variability.

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Replacing 6T SRAMs with 3T1D DRAMs in the l1 data cache to combat process variability.

Bibliographic Details
Main Author:	Liang, Xiaoyao
Other Authors:	Brooks, David, Canal, Ramon, Wei, Gu-Yeon
Format:	Article
Language:	Spanish
Subjects:	Dispositivos de almacenamiento Circuitos integrados Transistores Diodos Memoria caché Artículos de revista

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